commit	04c0fa81aca3da7fa05b71e2fabe0ac502cbe28b	[log] [tgz]
author	Git bot <[email protected]>	Wed Apr 20 00:19:11 2022 +0000
committer	Git bot <[email protected]>	Wed Apr 20 00:19:11 2022 +0000
tree	892c0d4b2b175294fd6eb1b0a9f7b824155cedb2
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Auto updated submodule references

caravel[diff]

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tree: 892c0d4b2b175294fd6eb1b0a9f7b824155cedb2

README.md

Amaranth+Coriolis Test SoC

This is a submission of a test SoC for MPW4 built from https://github.com/ChipFlow/mpw4

It contains:

Minerva RV32IM CPU
512 bytes SRAM
(Q)SPI flash for code and data memory using spimemio from picosoc
HyperRAM for RAM extension using a derivative of litehyperbus
8-bit GPIO
UART, timer, and interrupt controller

Built using:

Amaranth
Yosys+ABC
Coriolis for PnR; with PDKMaster and flexcell used in place of the standard sky130 cells.

	
		OSZAR »