commit	09cb718b3993b2f37105c9ccd20ed990f3da1f3b	[log] [tgz]
author	gatecat <[email protected]>	Sat Jan 22 21:43:27 2022 +0000
committer	gatecat <[email protected]>	Thu Mar 17 16:37:30 2022 +0000
tree	a9a44493ef483335b029d8e663bbbcf824a25098
parent	f1b093f4cc0b64e5ca4ad8830a8524bbdcf616cb [diff]

Add GDS and GL verilog

Signed-off-by: gatecat <[email protected]>

gds/user_project_wrapper.gds.gz[Added - diff]
verilog/gl/user_project_core_mpw5.v[Added - diff]
verilog/gl/user_project_wrapper.v[diff]

3 files changed

tree: a9a44493ef483335b029d8e663bbbcf824a25098

README.md

Amaranth+Coriolis Test SoC

This is a submission of a test SoC for MPW4 built from https://github.com/ChipFlow/mpw4

It contains:

Minerva RV32IM CPU
512 bytes SRAM
(Q)SPI flash for code and data memory using spimemio from picosoc
HyperRAM for RAM extension using a derivative of litehyperbus
8-bit GPIO
UART, timer, and interrupt controller

Built using:

Amaranth
Yosys+ABC
Coriolis for PnR; with PDKMaster and flexcell used in place of the standard sky130 cells.

	
		OSZAR »